1. Field of the Invention
This invention relates to a method of estimating the signal delay in a VLSI circuit and particularly to a method of feasibly fast calculating the delay and conversion time of a transmission signal in the VLSI circuit in order to prevent the erroneous logic judgment of a circuit design.
2. Description of Related Art
In a conventional technology, a method estimates the signal delay in an interconnection circuit by fixing the structure, number of components, and capacitance function of an interconnection network, but the technology could not be widely used in structures of different interconnection networks.
In a conventional technology that broke through the limit to the structure of a fixed interconnection network, a method feasibly estimates the transmission signal delay caused by components in two circuits, but it could not be used for calculating the total signal delay from input to output in a VLSI circuit.
Consequently, because of the technical defects described above and through wholehearted experience and research, the present invention was developed to effectively improve the defects described above.